1. Field
The present disclosure relates generally to memories, and more specifically, to dynamic control of memory access speed.
2. Background
Memory systems are used extensively today in digital systems to store data needed by various processing entities. A memory system generally includes a memory controller that manages access to memory. A typical memory generally has a matrix structure formed by rows and columns of memory cells, with each memory cell being capable of storing data. A memory cell may be accessed by a processing entity, or other source, by providing the appropriate row and column address to the memory controller. The row and column address may be sent over a bus with the row address occupying the lower-order bits and the column address occupying the higher-order bits on the bus. The row and column addresses will be collectively referred to herein as the “address.”
The memory controller may be used to generate the appropriate control signals for the memory from the address. More specifically, the memory controller may present a “row access strobe” to the memory to move an internal pointer to the appropriate row. This is generally thought of as opening a “page” in the memory. Once the page is opened, the memory controller may present a “column access strobe” to the memory to access a memory cell in the selected row. Thus, one can readily see that the delay associated with any memory operation depends on whether a processing entity is attempting to access an open or unopened page in the memory. If the processing entity is attempting to access an unopened page in the memory, the memory controller must present a row access strobe to the memory to move the pointer before presenting a column access strobe. If, on the other hand, the processing entity is attempting to access an open page in the memory, the memory controller needs only to present a column access strobe to the memory.
With the advent of more powerful processor based software programs, the demands on the memory have been increased. As a result, high performance memory systems with high speed access are becoming more commonplace in the market. These high performance memory systems tend to consume more power than lower performance memory systems. This is important in battery operated devices, such as cellular and wireless telephone, laptop, personal digital assistant (PDA), and the like. In these devices, as well as other applications, power saving concerns may dictate lower performance designs in terms of reduced memory access speed. These lower performance designs tend to increase battery life, but often result in one or more processing entities having to wait to access the memory.